Mac OS 9
Data Fields
ATADevConfig Struct Reference

#include <ATA.h>

Data Fields

SInt32 ataConfigSetting
 
UInt8 ataPIOSpeedMode
 
UInt8 reserved
 
UInt16 atapcValid
 
UInt16 ataRWMultipleCount
 
UInt16 ataSectorsPerCylinder
 
UInt16 ataHeads
 
UInt16 ataSectorsPerTrack
 
UInt16 ataSocketNumber
 
UInt8 ataSocketType
 
UInt8 ataDeviceType
 
UInt8 atapcAccessMode
 
UInt8 atapcVcc
 
UInt8 atapcVpp1
 
UInt8 atapcVpp2
 
UInt8 atapcStatus
 
UInt8 atapcPin
 
UInt8 atapcCopy
 
UInt8 atapcConfigIndex
 
UInt8 ataSingleDMASpeed
 
UInt8 ataMultiDMASpeed
 
UInt16 ataPIOCycleTime
 
UInt16 ataMultiCycleTime
 
UInt8 ataUltraDMASpeed
 
UInt8 reserved2
 
UInt16 ataUltraCycleTime
 
UInt16 Reserved1 [5]
 

Detailed Description

Bus timing config info passed between ATA Mgr and the AIM

Field Documentation

◆ ataDeviceType

UInt8 ATADevConfig::ataDeviceType

<–: Specifies the socket type (get config only) 00 = Unknown socket 01 = Internal ATA bus 02 = Media Bay 03 = PCMCIA

◆ ataHeads

UInt16 ATADevConfig::ataHeads

AIM's must return 0

◆ ataMultiCycleTime

UInt16 ATADevConfig::ataMultiCycleTime

<->:Cycle time in ms for PIO mode

◆ ataMultiDMASpeed

UInt8 ATADevConfig::ataMultiDMASpeed

<->: Single Word DMA Timing Class

◆ atapcAccessMode

UInt8 ATADevConfig::atapcAccessMode

<–: Specifies the device type (get config only) 00 = Unknown device 01 = standard ATA device (HD) 02 = ATAPI device 03 = PCMCIA ATA device

◆ atapcConfigIndex

UInt8 ATADevConfig::atapcConfigIndex

Reserved

◆ atapcCopy

UInt8 ATADevConfig::atapcCopy

Reserved

◆ atapcPin

UInt8 ATADevConfig::atapcPin

Reserved

◆ atapcStatus

UInt8 ATADevConfig::atapcStatus

Reserved

◆ atapcVcc

UInt8 ATADevConfig::atapcVcc

Reserved

◆ atapcVpp1

UInt8 ATADevConfig::atapcVpp1

Reserved

◆ atapcVpp2

UInt8 ATADevConfig::atapcVpp2

Reserved

◆ ataPIOCycleTime

UInt16 ATADevConfig::ataPIOCycleTime

<->: Multiple Word DMA Timing Class

◆ ataPIOSpeedMode

UInt8 ATADevConfig::ataPIOSpeedMode

<->: Configuration setting
Bits 3 - 0: Reserved Bit 4: Reserved
Bit 5: Reserved
Bit 6: ATAPIpacketDRQ 1 = Check for Interrupt DRQ on ATAPI command packet DRQ 0 = Default: Check only for the assertion of command packet DRQ Bits 31 - 7: Reserved

◆ ataRWMultipleCount

UInt16 ATADevConfig::ataRWMultipleCount

reserved

◆ ataSectorsPerCylinder

UInt16 ATADevConfig::ataSectorsPerCylinder

AIM's must return 0

◆ ataSectorsPerTrack

UInt16 ATADevConfig::ataSectorsPerTrack

AIM's must return 0

◆ ataSingleDMASpeed

UInt8 ATADevConfig::ataSingleDMASpeed

Reserved

◆ ataSocketNumber

UInt16 ATADevConfig::ataSocketNumber

AIM's must return 0

◆ ataSocketType

UInt8 ATADevConfig::ataSocketType

Reserved

◆ ataUltraCycleTime

UInt16 ATADevConfig::ataUltraCycleTime

reserved

◆ ataUltraDMASpeed

UInt8 ATADevConfig::ataUltraDMASpeed

<->:Cycle time in ms for Multiword DMA mode

◆ reserved

UInt8 ATADevConfig::reserved

<->: Device access speed in PIO Mode

◆ Reserved1

UInt16 ATADevConfig::Reserved1[5]

<-> Cycle time in ms for Ultra DMA mode

◆ reserved2

UInt8 ATADevConfig::reserved2

<-> Ultra DMA timing class bit-significant

The documentation for this struct was generated from the following file: